Eeprom memory including an error correction system

ABSTRACT

An electrically erasable and programmable memory includes a memory array having memory cells connected to word lines and bit lines. The bit lines are arranged in columns. The memory also includes read circuits connected to the bit lines and programming latches connecting the bit lines to a programming line. The memory includes a device to break the conductive paths connecting the memory cells of a column to the read circuits when data has been loaded into the latches of the column, without breaking the conductive paths that connect the latches of the column to the read circuits.

FIELD OF THE INVENTION

[0001] The present invention relates to electrically erasable andprogrammable memories, and, more particularly, to page-programmableEEPROM memories with an error correction system.

BACKGROUND OF THE INVENTION

[0002] In EEPROM memories, the value of a bit stored in the memory cellis represented by the value of the threshold voltage of a floating-gatetransistor which may be modified at will by erasing or programmingoperations. The programming or erasure of a floating-gate transistorincludes the injection or extraction of electrical charges into the gateof the transistor by tunnel effect (Fowler-Nordheim effect) using aprogramming/erasure high voltage Vpp in the range of 10 to 20 volts.

[0003] The reading of a memory cell having a floating-gate transistorincludes comparing the threshold voltage Vt of the transistor with areference voltage Vt0 that is substantially in the middle between thenegative threshold voltage of a programmed transistor and the positivethreshold voltage of an erased transistor. In practice, this comparisonis made by the application, to the transistor gate, of a read voltageVread that is substantially equal to Vt0 and then by observing whetherthe transistor is on or off. The on state or off state of the transistoris detected by a read circuit generally called a read amplifier (or“sense amplifier”), connected to the bit line to which the floating-gatetransistor is itself connected. During the reading process, an erasedtransistor remains off because its threshold voltage is higher thanVread. No current flows in the bit line and this corresponds byconvention to a bit equal to 0 at output of the read circuit (certainmemories use an opposite convention). A programmed transistor on thecontrary is On because its threshold voltage is below Vread. A currentflows in the bit line and this corresponds by convention to a bit equalto 1 at output of the read circuit.

[0004] It is assumed that the threshold voltage Vt of the transistorwill remain stable in time, normally for several years, under specifiedconditions of temperature and use. In other words, the electricalcharges injected into the gate of the transistor remain indefinitelytrapped therein so long as a reverse erasure operation is not performed,and the extracted electrical charges do not, in principle, return intothe erased gate so long as a reverse programming operation is notperformed. However, manufacturing defects may sometimes affect thestability of certain cells, occasionally leading to an error in thereading of a bit. For example, the negative threshold voltage of aprogrammed transistor may develop slowly towards a positive value higherthan Vread. There is then data corruption so that a “0” is read in thememory instead of the initially recorded “1”, or vice versa.

[0005] For this reason, the secured-type EEPROM memories are providedwith an error correction circuit that generates an error correctioncode, or ECC code, before each recording of a binary word. An ECC codeof this kind is concatenated with the binary word and recorded in thememory jointly with this word. When the word is then read in the memory,the ECC code that accompanies it makes it possible to detect thepresence, if any, of an erroneous bit in the word and to correct thebit.

[0006] The drawback of a secured memory, is that, for a given storagecapacity, it requires a number of memory cells that is appreciablygreater than that of a non-secured memory because a portion of thememory cells is reserved for the storage of the ECC code bits. To reducethe ratio between the number of cells designed for the storage of theECC codes and the number of cells receiving data bits, it isadvantageous to associate an ECC code with several binary words ratherthan to associate one ECC code with each binary word. Thus, for example,a Hamming code used to detect and correct a wrong bit in a bit stringmust include:

[0007] at least 4 bits for a string of 8 bits giving a total of 12 bitsto be recorded in the memory and a rate of occupation of memory space bycode bits equal to about 33%,

[0008] at least 5 bits for a string of 16 bits giving a rate ofoccupation of memory space by code bits of about 24%,

[0009] at least 6 bits for a string of 32 bits, giving a rate ofoccupation of memory space by code bits of about 16%, etc.

[0010] The association of an ECC code with a bit string comprisingseveral concatenated binary words is thus an advantageous solution forreducing the number of code bits in a memory. However, the implementingof a method for the concatenation of binary words designed to formstrings of very long bits containing an ECC code is hardly practical ina page programmable EEPROM memory.

[0011] Indeed, in a memory of this kind, the number of programminglatches must be identical to the number of bits in a page to enable thesimultaneously recording of an entire page. When a specified binaryaddress word has to be recorded within a bit string comprising otherbinary words and an ECC code, it is necessary to read the complete bitstring in the memory, insert the binary word therein by crushing theformer word with the same address, compute a new ECC code and insert thenew ECC code in overwriting the former ECC code. The new bit stringcomprising the new binary word and the new ECC code is then loaded intothe programming latches. However, if another word of the same bit stringhas to be then replaced by a new word before the activation of theprogramming step, it is no longer possible to access the bit string ifit has been loaded into the latches.

[0012] To overcome this drawback, a standard approach includes thetemporary storage of the bit strings in a read and write accessiblebuffer register before the loading of the latches. So long as the bitstrings are in the buffer register, they can be modified at will withthe insertion of a new ECC code at each modification. The drawback ofthis approach lies in the very existence of the buffer register whichrequires considerable space and makes the memory more complicated andcostly to make. Thus, for example, a memory comprising pages of 128binary words recorded in pairs of words accompanied by an ECC coderequires a buffer register capable of the storage, before the loading oflatches, of the 128 binary words of the page with, in addition, theassociated ECC codes.

SUMMARY OF THE INVENTION

[0013] The present invention seeks to overcome this drawback. Moreparticularly, the present invention is aimed at obtaining a pageprogrammable memory structure that does not require any buffer registerfor the storage of a page to be recorded, providing for, however, themodification of the bit strings as many times as is necessary before theprogramming process is begun.

[0014] To achieve this goal, the present invention is based on the factthat the programming latches of a memory are, like the memory cells,connected to the read circuits via the bit lines. The present inventionis also based on the fact that the On or Off state of a latch,considered between the connection point of a latch to a bit line and itspoint of connection to the programming line, is a function of dataelement that is loaded into the latch. The idea of the present inventionis thus to use the read circuits to read the contents of the latches, byapplying the memory cell reading principle to the latches. To this end,another idea of the present invention is to cut the conductive pathsconnecting the read circuits to the memory cells when the latches haveto be read, so that the On or Off state of the memory cells does notinterfere with the reading of the latches. Thus, the row of latchespresent in the memory may be used as a read accessible and writeaccessible buffer register for the storage and modification, at will, ofthe bit strings to be recorded before the activation of the programmingprocess.

[0015] More specifically, the present invention provides for a memory ofthe type described here above, including breakable conductive pathsconnecting the memory cells of a column to the read circuits when datahas been loaded into the latches of the column, without breaking theconductive paths that connect the latches of the column to the readcircuits.

[0016] According to one embodiment, the memory comprises a switchingdevice arranged on the bit lines between the memory array and thelatches, and a controller for the switching device arranged to open theswitching device of a column when data has been loaded into the latchesof the column. According to one embodiment, the controller comprises amemory circuit delivering a signal to open the switching device of thecolumn after having received a signal for loading the latches of thecolumn.

[0017] According to one embodiment, the memory circuit is an element ofa column selection circuit. According to one embodiment, the switchingdevice of a column that is set in the open state in read mode is closedagain in programming mode by a resetting signal applied to thecontroller. According to one embodiment, a switching device includes twoparallel-connected switches, the first switch being driven by thecontroller, the second switch being driven by a signal providing for theclosure of the second switch when the memory is in programming phase andfor its opening if not.

[0018] According to one embodiment, the memory comprises symmetricallystructured latches that can receive bits equal to 1 or 0 withoutrequiring a resetting of the latches. According to one embodiment, thecells of one and the same column connected to one and the same word linecomprise a bit string formed by at least two binary words and one errorcorrection code. According to one embodiment, the memory comprises aprogramming and error correction circuit arranged to perform thefollowing operations upon the reception of a word to be recorded in thememory array at a specified address: the reading in the memory array ofthe bit string designated by the address of the word to be recorded, theinsertion of the binary word into the bit string and the computation ofa new error correction code, and the loading of the new bit string intothe latches of the column designated by the address of the word to berecorded.

[0019] According to one embodiment, the programming and error correctioncircuit is arranged to perform the following operations upon thereception of a binary word to be recorded in a bit string that has beenloaded beforehand into the latches: reading the bit string loaded intothe latches via the read circuits, inserting the binary word into thebit string and computing a new error correction code and loading the newbit string into the latches.

[0020] The present invention also relates to a method for the recordingof the binary words into an electrically erasable and programmablememory of the type described here above, comprising the loading, intothe latches of a column, of a bit string comprising at least two binarywords and breaking the conductive paths connecting the memory cells ofthe column to the read circuits without breaking the conductive pathsthat connect the corresponding latches to the read circuits. The methodalso includes reading the bit string loaded into the latches via theread circuits, replacing a binary word by another in the bit string andloading the new bit string into the latches.

[0021] According to one embodiment, a bit string comprises an errorcorrection code that is recomputed when a new binary word is insertedinto the bit string and that is inserted into the bit string instead ofthe initial error correction code.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] These object, features and advantages of the present inventionwill be explained in greater detail in the following description of amemory structure and of the method according to the invention, withreference to the appended figures.

[0023]FIG. 1 is a schematic diagram showing the general architecture ofa memory according to the invention.

[0024]FIG. 2 is a more detailed electrical diagram of various elementblocks in FIG. 1.

[0025]FIG. 3 is a schematic diagram showing the general architecture ofa secured memory according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026]FIG. 1 shows the structure of a page programmable EEPROM memoryaccording to the invention. The memory 10 has a memory array 11comprising memory cells Cj arranged in matrix form, connected to wordlines WLi and bit lines BLj. The bit lines BLj are arranged in columnsCOLk and the memory array 11 has a repetitive structure at each newcolumn. Each column COLk herein has 21 bit lines BL0 to BL20 and thus,in combination with a word line WLi, it defines groups of 21 cells C0 toC20 allowing the storage of 21-bit strings each comprising two 8-bitbinary words (bytes) Wl, W2 and-an ECC or error correction code. On eachword line WLi, the groups of cells C0 to C20 of each column COLk areselected via a column selection transistor CGT_(k), or gate controltransistor, schematically shown in FIG. 1. For the sake of thereadability of FIG. 1, only the first column COL0 and the two first wordlines WL0, WL1 of the memory array 11 are shown. Also, the cells C0 toC20 of the first column and the corresponding bit lines are not allshown.

[0027] Again, in a standard way, each bit line BLj of each column isconnected to a common programming line 12 via a programming latch LTjand each transistor CGTk is connected to a gate control line 13 via acolumn selection circuit LTCGk. Each programming latch LTj has an inputconnected to a j ranking wire of a data bus 14, herein having 21 wiresfor the application, to the 21 latches of a column, of the bits b0 tob20 of a bit string to be recorded in the memory.

[0028] In programming mode, the common line 12 is used to apply theprogramming signal WRITE to the bit lines BLj whose latches LTj are inthe On state, the WRITE signal formed by a programming high voltagepulse Vpp. In read, erasure or programming mode, the line 13 is used forthe application, to the transistors CGTk whose latches LTCGk are in theOn state, of a gate control voltage VCG used for the activation andselection of the corresponding columns.

[0029] The memory 10 also comprises 21 read circuits SA0 to SA20 (“senseamplifiers”) to read the 21 bits of a bit string selected in read mode.Each bit line BLj of each column COLk is connected to a read circuit SAjof a corresponding rank via a selection transistor TSj, a readtransistor TRj and a read bus RB. The bus RB provides for theinterconnection of the same-ranking bit lines BLj to one and the sameread circuit SAj. The selection transistors TSj (TS0 to TS20) of the bitlines of one and the same column COLk are driven by a common signal SELkdelivered by a pre-decoder PDEC. The pre-decoder PDEC receives, atinput, the least significant part ADL of the addresses applied to thememory 10 and, with the selection transistors TSj, forms a columndecoder CDEC. Each k ranking selection signal SELk delivered by thepre-decoder PDEC is also applied to the latches LTj of a same rankingcolumn COLk and to the selection circuits LTCGk of this column. The mostsignificant address bits ADH of the addresses applied to the memory areapplied to a row decoder RDEC whose outputs control the various wordlines WLi. The read transistors TRj (TR0 to TR20) are driven by a signalREAD identical for all the columns.

[0030] Thus, the conductive path connecting the memory cells Cj of a bitline BLj to a read circuit SAj conventionally comprises a selectiontransistor TSj and a read transistor TRj. According to the invention,the memory 10 further comprises insulation transistors TIj used asswitching device and arranged on the bit lines, between the memory array11 and the nodes for connection to the bit lines of the latches LTj.More particularly, each column COLk comprises 21 transistors TI0 to TI20arranged on the bit line BL0 to BL20. The opening of the transistors TIj(Off state) of a column has the effect of cutting off the conductivepaths connecting the cells Cj of the column to the read circuits SAj, sothat only the latches LTj remain electrically connected to the readcircuits SAj. According to the invention, the transistors TIj allow theuse of the read circuits SAj to read data b0 to b20 loaded into thelatches LTj of a selected column, as shall be described in greaterdetail further below.

[0031]FIG. 1 shows that the latches LTj are also connected to a line 15through which a supply voltage VA is applied to them, a line 17 throughwhich a loading signal LOAD is applied to them and a line 18 throughwhich a reset signal RST1 is applied to them. The circuits LTCGk areconnected to the line 15, a line 19 through which a resetting signalRST2 is applied to them and a line 20 through which a signal RW isapplied to them.

[0032]FIG. 2 shows a more detailed view of the structure of the memorycells Cj, programming latches LTj and circuits LTCGk. Each cell Cjconventionally has a floating-gate transistor FGT and an accesstransistor. The access transistor TA has its gate G connected to a wordline WLi, its drain D connected to a bit line BLj and its source 3connected to the drain D of the transistor FGT. The transistor FGT hasits gate G connected to a gate control line CGL and its source Sconnected to a source line SL. The line CGL is common to all thetransistors FGT of the cells Cj of one and the same column COLk and of asame bit line WLi to form the 21-cell groups mentioned here above. Theline CGL is connected to a column selection line CLk via a gate controltransistor CGTk, whose gate is connected to the word line WLi. Theselection line CLk is connected to the line 13 described further abovevia the selection circuit LTCGk.

[0033] The circuit LTCGk connects the line 13 to the line CLk via twoparallel-connected transistors T1, T3. The transistor T1 is driven bythe signal RW and the transistor T3 is driven by the output of aninverter cell with memory INV1 comprising two inverter gates whoseoutputs are reciprocally brought to the inputs, the cell INV beingelectrically supplied by the voltage VA (line 15). The output of thecell INV1 is grounded via a transistor T4 driven by the resetting signalRST2. The input of the cell INV1 is grounded by two series-connectedtransistors T5, T6 respectively driven by the signals LOAD and SELk.

[0034] Thus, the drain D of a floating-gate transistor FGT of a memorycell Cj is connected to a read amplifier SAj via an access transistorTA, an insulation transistor TIj according to the invention, theselection transistor TSj of a column decoder CDEC and a read transistorTRj. The transistors TSj and TRj are respectively driven by the signalsSELk and READ described further above and the transistor TIj is drivenby a signal BRK. According to the invention, the signal BRK is hereintaken at the input of the cell INV1 of the selection circuit LTCGk. Thesignal BRK is thus the reverse of the signal that drives the transistorT3 so that the transistor TIj is always off when the transistor T3 is onand is always on when the transistor T3 is off.

[0035] The bit line BLj is connected to a line 12 that uses a transistorT10 of the programming latch LTj to deliver the signal WRITE. Thetransistor T10 has its drain D connected to the line 12 and its source Sconnected to the bit line BLj in a node located between the insulationtransistor TIj and the selection transistor TSj.

[0036] In the latch LTj, the gate of the transistor T10 is driven by aninverter cell with memory INV2 which, like the cell INV1, comprises twoinverter gates connected back to front and supplied with the voltage VA.The input of the cell INV2 is connected to the ground by threeseries-connected transistors T11, T12, T13. The gate of the transistorT11 is connected to a wire of the data bus 14 to receive a data bit bjduring a loading operation. The transistor T12 is driven by the signalLOAD and the transistor T13 is driven by the signal SELk. The output ofthe inverter cell INV2 is connected to the ground by three transistorsT14, T15, T16. The gate of the transistor T14 is connected to the gateof the transistor T11 via an inverter gate. The transistor T15 isdriven, like the transistor T12, by the signal LOAD and the transistorT16 is driven, like the transistor T13, by the signal SELk. Thissymmetrical structure of the latch LTj, which is an optional structure,is used for the recording at will of the bits at 0 or at 1 in the latchwithout requiring a resetting of the latch. The resetting of the latchis done by a transistor T17 driven by the signal RST1, connected betweenthe output of the cell INV2 and the ground.

[0037] The operation of the memory 10 can be distinguished from that ofa conventional memory by the fact that the latches LTj of a column COLkselected via a signal SELk are read accessible via the read circuit SAjwhen data has been loaded into the latches. During the loading step, thebits b0 to b20 are applied to the latches LTj, the voltage VA is equalto the supply voltage Vcc of the memory Vcc, a signal SELk for theselection of a k ranking column is taken to 1 and the loading signalLOAD is also taken to 1. The output of the cell INV2 of each latch LTjof the selected column COLk copies the value of the bit bj applied tothe latch. The simultaneous passage to 1 of the signals LOAD and SELkcauses the output of the cell INV1 in the selection circuit LTCGk toswitch over to 1, so that the transistor T3 is on. At this time, thesignal BRK goes to 0 and the insulation transistors TIj of the selectedcolumn are turned off, thus insulating the memory cells of the selectedcolumn of the read circuits SAj.

[0038] In practice, a step of this kind for loading the latches of acolumn may be applied sequentially to all or part of the columns of oneand the same word line for the complete or partial loading of a page.Through the invention, the loading step may be followed by a step ofreading the latches LTj via the read circuits SAj. Indeed, the outputtransistor T10 of each latch LTj is respectively on when a bit bj equalto 1 has been loaded into the latch and off when the bit bj equal to 0has been loaded. The On or Off state of a latch therefore representsdata loaded into the latch. Thus, the latches may be read by activatingthe read circuits SAj and by taking the signals SELk and READ to 1 as inthe case of a standard reading of the memory. For the reading of thelatches, the line 12 must be grounded. When a bit at 1 has been loadedinto a latch LTj, a read current Iread goes through the transistor T10of the latch as indicated by an arrow A1 and the output of thecorresponding read circuit SAj goes to 1. If not, the output of the readcircuit SAj remains at 0. The reading principle is thus the same as forthe reading of the floating-gate transistors of the memory cell Cj whichare herein insulated from the read circuits SAj by the transistors TIjduring the reading of the latches. The latches LTj may thus be read andrewritten as desired before the activation of the process of erasing andprogramming the memory cells. Furthermore, the symmetrical structure ofthe latches enables data to be rewritten therein at 1 or at 0 withoutrequiring any resetting of the latches via the signal RST1.

[0039] It can be noted here that the read circuits SAj do not “know” ifthey are reading memory cells or latches. The activation of an operationof reading a column COLk automatically leads to a reading of the latchesof the column or a reading of the memory cells of the column, dependingon whether data has been loaded or not into the latches. If data has notbeen loaded into the latches, the read current Iread flows in theselected cells Cj as indicated by an arrow A2. So that the reading maybe done automatically in the memory array 11, when data has not beenloaded into the latches, the signal RW applied to the selection circuitsLTCGk is taken to 1 and the read voltage Vread is applied to the line13.

[0040] With reference to the problem explained above, this possibilityof reading latches offered by the present invention allows the recoveryof a bit string present in the latches, the insertion therein of a newbinary word, the computation of a new ECC code and the reinjection ofthe bit string into the latches. A secured memory architecture usingthis characteristic will be described further below.

[0041] The following steps of erasure and programming of the memorycells are obtained after the final loading of the latches when data nolonger has to be modified. The cells that have to receive new data areerased by applying the voltage Vpp (10 to 20 volts) to the word line WLiselected by the row decoder RDEC as well as to the programming line 13(voltage VCG) and the supply line 15 (voltage VA), the source line SL ofthe floating-gate transistors FGT being connected to the ground. Thevoltage Vpp is found at the gates of all the transistors FGT of thecolumns (of the selected word line Wli) whose programming latches LTjhave been loaded with data because the circuit LTCGk of these columns,which has received the signal LOAD during the loading step, is on. Thesetransistors FGT are thus erased collectively.

[0042] At the programming step, the column selection circuits LTCGk arereset via the signal RST2 to reopen the conductive paths connecting thelatches LTj to the memory cells Cjj. The latches LTj themselves are notreset because they contain the programming data. The voltage Vpp isapplied to the selected word line WLi, the voltage VCG is taken to theground, the signal RW is taken to the voltage Vcc to let through the “0”(ground) at the gates of the transistors FGT of the word line. Thesignal WRITE formed by a pulse of the voltage Vpp is sent. The latchesin the On state (having received a bit at 1) let through the voltage Vppup to the drain of the transistors FGT which are then programmed (withthe injection of electrical charges).

[0043] The present invention can of course have several alternativeembodiments. In particular, the signal BRK that opens the insulationtransistors TIj of a column may be delivered by any memory cell, whetheror not an inverter, whose output is taken to 0 by the combination of thesignals LOAD and SELk and set at 1 by the signal RST2. The use of thecells INV1 of the column selection circuit LTCGk to generate the signalBRK has not been planned here except with a view to saving resources.

[0044] Furthermore, a variant of the present invention includesplanning, in parallel with the insulation switches TIj, for closingswitches TOj shown in dashes in FIG. 2. These closing switches TOj aredriven by a WRITE-ENABLE signal that is set at 1 during the programmingoperation. In this case, it is not necessary to provide for a signalRST2 distinct from the signal RST1 to close again (turn on) thetransistor TIj during the programming step. The passage of the voltageVpp to the memory cells is herein provided by the transistors TOj andthe transistors TIj can remain off. Furthermore, in this embodiment, thetransistor T1 present in the circuits LTCGk may be driven by the signalREAD.

[0045]FIG. 3 illustrates an application of the present invention to themaking of a secured page programmable memory 30, with serial input andoutput. The memory 30 shown in schematic form comprises the memorystructure 10 that has just been described, a central processing unitCPU, register RDIN and RAIN with serial input and parallel output and anoutput register RDOUT with parallel input and serial output. The centralprocessing unit CPU has a standard type of error correction algorithmtaking the form of a wired logic circuit ECCCT. This circuit ECCCT isdesigned to automatically correct an erroneous bit in a bit string givenat its input E1 and/or generate an ECC code from a string of data bitsgiven at its input E2. The memory 10, as described further above, has amemory array 11, a stage TI (comprising the insulation switches TIjaccording to the invention), a data loading stage LT (comprising thelatches LTj), the column decoder CDEC, a stage TR (comprising the readtransistors TRj), a read bus RB and a read stage SA (comprising the readcircuits SAj). The serial inputs of the register RDIN and RAIN areconnected to an input port PIN of the memory 30 and the serial output ofthe register RDOUT is connected to an output port POUT.

[0046] The operation codes CODEOP of the operations to be performed arereceived in the register RDIN and applied to the central processing unitCPU for decoding and execution. The word-recording addresses arereceived in the register RAIN and applied to the memory 10. Moreparticularly, the most significant address bits ADH are applied to therow decoder RDEC and the least significant address bits ADL are appliedto the column decoder CDEC except for the least significant address bitA0 applied to the unit CPU. The binary words Wj to be recorded in thememory are received in the register DRIN and are applied to the centralprocessing unit CPU which delivers, to the input of the stage LT,strings of bits of the binary words concatenated in pairs andaccompanied by an ECC error correction code. According to the invention,the central processing unit CPU uses the stage of latches LT as aread-accessible and write-accessible dynamic register to store bitstrings to be recorded in the memory array 11 and to modify them if needbe before the activation of the erasure and programming processes.

[0047] For example, it will be considered that the central processingunit CPU receives the following write instruction in the form of asequence of bytes:

[0048] [CODEWRITE][ADH1][ADL1 ][W1][ADL2 ][W2][ADL3][W3]

[0049] This instruction means: “in the address word line ADH1, write theword W1 in the address column ADL1, the word W2 in the address columnADL2 and the word W3 in the address column ADL3”. To highlight theadvantages of the present invention, it will also be assumed that thewords W1 and W3 have the same partial address, namely that the recordingaddresses ADL1, ADL3 of the words W1, W3 are identical, except for thebit A0. These addresses thus corresponds physically to the same bitstring in the same physical column of the memory array.

[0050] After having decoded the instruction code CODEWRITE, the centralprocessing unit CPU applies the bits A15-A8 of the address ADH1 to thedecoder RDEC and the 7 most significant bits A7-A1 of the address ADL1to the decoder CDEC, the bit A0 being not applied to the decoder CDEC.The address ADH1 (A15-A8) which designates the page (word line) will notbe modified until the end of the page loading and programming process.The unit CPU then reads the word W1 received in the register RDIN andreads the bit string presented in the physical address column A7-A1 viathe read circuit SA:

[0051] Wa//Wb//ECC

[0052] The central processing unit CPU then uses the code ECC to verifythe validity of the bits of the string and, if necessary, corrects anerroneous bit. Then, the unit CPU replaces one of the words Wa, Wb bythe new word W1, the word Wa or Wb to be replaced being designated bythe address bit A0. This is for example a word Wa if the bit A0 is equalto 0 (even parity address). The unit CPU computes the new ECC′ code as afunction of the bits of the words W1 and Wb and delivers a new bitstring:

[0053] W1//Wb/ECC′

[0054] This new bit string is applied to the input of the stage LT andis loaded into the latches of the address column A7-A1 via the signalLOAD. The central processing unit CPU performs the same steps for thewords W2 and W3. However, when these steps are achieved for the word W3which has the same partial address A7-A1 as the word W1, the bit stringdelivered by the read circuit SA is not the bit string Wa//Wb//ECCpresent in the memory but the bit string W1//Wb//ECC′ previously loadedinto the latches of the column of the stage LT designated by the addressA7-A1. Indeed, as seen further above, the path connecting the readcircuit SA to the memory array 11 has been cut by the stage TI after theloading of the string W1//Wb//ECC′ and the read circuit SA can read onlythe contents of the stage LT. The central processing unit CPU thusreplaces the word Wb by the word W3, computes a new code ECC′ and loadsthe new bit string into the same latches of the stage LT:

[0055] W1//W2/ECC″

[0056] The simplified example that has just been described shows thatthe memory 30 requires no buffer register other than the stage LT. Thisexample also shows that the memory can work in page overflow mode, i.e.it can receive a quantity of words to be recorded in a page that isgreater than the capacity of a page, in overwriting words already loadedinto the stage LT with new words received (while at the same timerecomputing appropriate ECC codes) until the process of erasure andprogramming of the memory cells is activated.

[0057] Table 1 here below describes and summarizes the basic steps of aprocess of loading and programming a page according to the invention.Although the step 3 of the table refers to the “reading of a bit stringin the memory”, it is quite clear that, in the light of the aboveexplanations, this reading is actually done in the latches of the columnbeing considered if a bit string has already been loaded into theselatches during a previous step.

[0058] The operation, in read mode, of the memory 30 is conventional perse. When a word Wj has to be read at a specified address, the stringWj//Wj+1//ECC designated by the partial address of the word Wj is readin the memory array, the step of verification and possible correction oferror is performed by the unit CPU via the circuit ECCCT, and the unitCPU delivers the two words Wj, Wj+1. The word Wj is selected from amongthe two words Wj, Wj+1 via a multiplexer MUX driven by the address bitA0, and is then placed in the register RDOUT and delivered to the outputport POUT in the form of serial data.

[0059] The present invention is of course applicable to the recording ofbit strings comprising three, four, five or even more binary words,provided of course that the number of bit lines contained in the columnsof the memory array is designed to receive such bit strings. The presentinvention is also applicable to various types of memory, serial accessor parallel access. Furthermore, although the problem described in theintroduction concerns secured memories and the insertion in securedmemories of bit strings comprising concatenated binary words and an ECCcode, the present invention is also applicable to non-secured memories,for example if it is desired to carry out a verification of the wordsloaded into the latches LT before the activation of the erasure andprogramming process. TABLE 1 (recording of a memory page) StepDescription of the step Next Step 1 Reception of the most significant

2 address bits ADH and application to the row decoder RDEC 2 Receptionof the less significant

3 address bit ADL and application to the column decoder CDEC 3 Readingin the memory of a bit string

4 Wa//Wb//ECC at the partial address ADH//ADL (without the bit A0) 4Analysis of the bit string for error Yes

5 detection. Detection of an erroneous No

6 bit? 5 Correction of the erroneous bit

6 6 Reception and reading of a word Wc

7 that has to be registered at the address ADH-ADL 7 Computation of anew ECC′ code from

8 the new pair of words Wc//Wb or Wa//Wc (depending on the value of theaddress bit A0) 8 Loading the bit string Wc//Wb//ECC′

9 or Wa//Wc//ECC′ into the latches LTj of the address ADL column 9 Newcolumn address received? Yes

2 No

10 10 Simultaneous erasure of all the cells

11 of the word line whose latches LT have been loaded with data 11Simultaneous programming of the cells END in the erased columns (WRITEpulse)

That which is claimed is:
 1. An electrically erasable and programmablememory comprising a memory array comprising memory cells connected toword lines and bit lines, the bit lines being arranged in columns, thememory also comprising read circuits connected to the bit lines andprogramming latches connecting the bit lines to a programming line,wherein the memory comprises means to break the conductive pathsconnecting the memory cells of a column to the read circuits when datahas been loaded into the latches of the column, without breaking theconductive paths that connect the latches of the column to the readcircuits.
 2. A memory according to claim 1, comprising switching meansarranged on the bit lines between the memory array and the latches, andmeans to control the switching means arranged to open the switchingmeans of a column when data has been loaded into the latches of thecolumn.
 3. A memory according to claim 2, wherein the control meanscomprise a memory circuit delivering a signal to open the switchingmeans of the column after having received a signal for loading thelatches of the column.
 4. A memory according to claim 3, wherein thememory circuit is an element of a column selection circuit.
 5. A memoryaccording to one of the claims 2 to 4, wherein the switching means of acolumn that are set in the open state in read mode are closed again inprogramming mode by a resetting signal applied to the control means. 6.A memory according to one of the claims 2 to 4, wherein a switchingmeans comprises two parallel-connected switches, the first switch beingdriven by the control means, the second switch being driven by a signalproviding for the closure of the second switch when the memory is inprogramming phase and for its opening if not.
 7. A memory according toone of the claims 1 to 6, comprising symmetrically structured latchesthat can receive bits equal to 1 or 0 without requiring a resetting ofthe latches.
 8. A memory according to one of the claims 1 to 7, whereinthe cells of one and the same column connected to one and the same wordline comprise a bit string constituted by at least two binary words andone error correction code.
 9. A memory according to claim 8, comprisinga programming and error correction circuit arranged to perform thefollowing operations upon the reception of a word to be recorded in thememory array at a specified address: the reading in the memory array ofthe bit string designated by the address of the word to be recorded, theinsertion of the binary word into the bit string and the computation ofa new error correction code, the loading of the new bit string into thelatches of the column designated by the address of the word to berecorded.
 10. A memory according to claim 9, wherein the errorprogramming and correction circuit is arranged to perform the followingoperations, upon the reception of a binary word to be recorded in a bitstring that has been loaded beforehand into the latches: reading the bitstring loaded into the latches via the read circuits, inserting thebinary word into the bit string and computing a new error correctioncode, loading the new bit string into the latches.
 11. A method for therecording of the binary words into an electrically erasable andprogrammable memory comprising a memory array comprising memory cellsconnected to word lines and bit lines, the bit lines being arranged incolumns, the memory also comprising read circuits connected to the bitlines and programming latches connecting the bit lines to a programmingline, the method comprising a step of loading, into the latches of acolumn, of a bit string comprising at least two binary words, whereinthe method further comprises the steps of: breaking the conductive pathsconnecting the memory cells of the column to the read circuits withoutbreaking the conductive paths that connect the corresponding latches tothe read circuits, reading the bit string loaded into the latches viathe read circuits, replacing a binary word by another in the bit stringloading the new bit string into the latches.
 12. A method according toclaim 11, wherein a bit string comprises an error correction code thatis recomputed when a new binary word is inserted into the bit string andthat is inserted into the bit string instead of the initial errorcorrection code.